In general, semiconductor memory devices used for storing data are divided into two types: volatile and nonvolatile. A volatile memory device loses stored data when the power supply is interrupted, while a nonvolatile memory device maintains the stored data when the power supply is interrupted. Therefore, in applications where the power supply is not always continuous, occasionally interrupted, requires the use of low power on occasion, such as in a mobile communication system, a memory card for storing music and/or image data, and/or other applications, nonvolatile memory devices are generally more widely used.
Typically, a nonvolatile device is formed using a stacked gate in which a gate insulating layer, a floating gate electrode, an inter-gate insulating layer, and a control gate electrode are sequentially stacked. In some implementations, a nonvolatile memory device may be formed by including a silicon layer in which a channel area is formed, an oxide layer in which a tunneling layer is formed, a nitride layer used as a charge trapping layer, an oxide layer used as a blocking layer, and/or a silicon layer used as a control gate electrode. Hereinafter, the above-mentioned layers will be terms a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure. Some implementations configure the nitride layer, which functions as the charge trapping layer, so that it overlaps with only a portion of the silicon layer, which is used as the control gate electrode. It is generally known that operations of a nonvolatile memory device having a local SONOS structure may be improved based on the adjustment of the length of the overlapping portion of the charge trapping layer and the gate electrode.
FIGS. 1 through 4 are sectional views of a conventional method for fabricating a nonvolatile memory device having a local SONOS structure. As shown in FIG. 1, an ONO layer 110 is formed on a silicon substrate 100 and a first photoresist layer pattern 121 is formed on the ONO layer 110. The ONO layer 110 has a structure in which a first oxide layer 111, a nitride layer 113 and a second oxide layer 115 are sequentially stacked. The first photoresist layer pattern 121 has an opening that exposes a part of a surface of the second oxide layer 115. Etching is performed by using the first photoresist layer pattern 121 as an etching mask to sequentially remove exposed parts of the second oxide layer 115, the nitride layer 113, and the first oxide layer 111. Then, as shown in FIG. 2, a part of a surface 101 of the silicon substrate 100 is exposed and ONO layer patterns 110′ are formed on both sides of the exposed surface 101, respectively. After etching is complete, the first photoresist layer pattern 121 is removed.
As shown in FIG. 3, a third oxide layer 130 is formed as a gate insulating layer on the exposed surface 101 of a silicon substrate 100 as shown in FIG. 2 by performing an oxidation process. A polysilicon layer 140 and a second photoresist layer pattern 122 are sequentially formed on the ONO layer pattern 110′ and the third oxide layer 130. Etching is performed using the second photoresist layer pattern 122 as an etching mask to remove exposed parts of the polysilicon layer 140 and the ONO layer pattern 110′. After etching is complete, the second photoresist layer pattern 122 is removed and then a polysilicon layer pattern 142, which is to be used as the control gate electrode, is formed as shown in FIG. 4. In addition, on both sides of the polysilicon layer pattern 142, a tunneling layer 112, a charge trapping layer 114, and a blocking layer 116 are formed so as to be arranged at the sides of the polysilicon layer pattern 142 and to be sequentially stacked on the silicon substrate 100. “A” denotes the length of an overlapping portion of the charge-trapping layer 114 and the polysilicon layer pattern 142. A source region 162 and a drain region 164 are formed respectively in a predetermined area of an upper portion of the silicon substrate 100 by performing, for example, an ion implantation using the polysilicon layer pattern 142 and a predetermined mask layer pattern (not shown) as an ion implantation mask.
As described above, according to a conventional method of fabricating a nonvolatile memory device, the length of the overlapping portions of the charge trapping layer 114 and the polysilicon layer pattern 142, “A,” is determined by the first photoresist layer pattern 121 as shown in FIG. 1 and the second photoresist layer pattern 122 as shown in FIG. 3. Accordingly, as the degree of integration of a device increases, the susceptibility to misalignment in photolithographic processing increases. Thus, the length “A” may become irregular depending on the specific positioning. Irregularity in the length of “A” may result in irregular characteristics of a memory cell, which may ultimately degrade the reliability of a memory device.